In recent years, a semiconductor device to be used with an electronic equipment such as, for example, a Large Scale Integration (LSI) is integrated in a large scale, and a processor, a bus, a memory and so forth which are conventionally used individually as individual elements can be incorporated on one chip.
Generally, the object of the integration into one chip resides in downsizing, cost down and reduction in power consumption. Such a semiconductor device as described above is called system LSI or System on Chip (SoC).
However, increase of functions to be incorporated in such a semiconductor device (hereinafter referred to sometimes as LSI or system LSI) as described above gives rise to a demerit that it increases the difficulty of the design. Most part of the difficulty originates from the fact that, by integration into one chip, a hardware architecture determined once cannot be easily changed later.
Particularly, in order to press onward with downsizing and cost down, reduction of the processing load to the system LSI and reduction of the margin on the design are required, and a performance verification technique at a first stage of the design is important to solve the problem described above.
The performance verification of a system LSI or the like is carried out after provisional decision is carried out regarding whether a function which a system has is to be implemented by hardware or software.
Generally, the software is described in the C language, an assembly language or some other language, and operation of the software can be simulated by execution on an actual apparatus model including a target processor or an Instruction Set Simulator (ISS) for a target processor.
Further, regarding operation of the hardware, simulation can be carried out by description using the Register Transfer Level (RTL), the Transaction Level Model (TLM), or both of the RTL and the TLM. It is to be noted that a representative RTL is the Verilog-HDL and a representative TLM is the System C.
In this manner, evaluation of a performance such as a processor load ratio can be carried out by simulating the entire system including both of the software and the hardware.
It is to be noted that also a technique is conventionally available wherein simulation is executed in order to create software (application) (for example, refer to Japanese Patent Laid-Open No. 2002-215423 and Japanese Patent Laid-Open No. 2006-59108).
An example of a conventional performance evaluation simulation apparatus for a semiconductor device is shown in FIG. 14. In the conventional simulation apparatus 100, a Central Processing Unit (CPU) 101, an I-cache (instruction cache) 102, a D-cache (data cache) 103, a bus 104, an external RAM (Random Access Memory) 105 and peripheral HW (HardWare) 106 are implemented by a hardware model.
It is to be noted that the CPU 101 includes an ISS 110 for executing software, an access processing section 111 for executing access to the outside and a data totalization section 112 for totalizing statistical information 120 as a result of simulation.
However, the conventional simulation apparatus 100 executes software 122 to be actually incorporated in the processor and based on specifications 121 as described above on the ISS 110. Therefore, in order to carry out the verification with high accuracy, a sufficient degree of completeness of the software 122 is required, and examination for optimization, that is, performance evaluation simulation, cannot be carried out at an early stage of the design.
Further, where the simulation is executed, there is a problem that the ISS 110 occupies the greater part of the simulation and the execution time becomes very long.
Therefore, a technique is conventionally available wherein software to be executed on a processor is modeled using a UML analysis to produce software so as to allow verification at an early stage of the design. Also another technique is conventionally available wherein a function model and software are produced from requested specifications or a conceptual model (refer to, for example, Japanese Patent Laid-Open No. 2001-318812 and Japanese Patent Laid-Open No. 2007-310449, hereinafter referred to as Patent Documents 3 and 4, respectively).
However, since such techniques as disclosed in Patent Documents 3 and 4 involve modeling of an application program from a document of requested specifications, a considerable number of man-hours are required before production of software and much time is required.
Further, since estrangement from software to be actually incorporated, or in other words, accuracy of a performance verification environment, is not known in such techniques as disclosed in Patent Documents 3 and 4, it is not known whether produced software is reliable.